RS4 RS3 RS2 RS1 RS0, OnCE Register Addressing | Motorola DSP56000

OnCE CONTROLLER AND SERIAL INTERFACE

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R/W GO

EX

RS4 RS3 RS2 RS1 RS0

Figure 10-4 OnCE Command Register

10.3.1.1Register Select (RS4-RS0) Bits 0-4

The Register Select bits define which register is source (destination) for the read (write) operation. Table 10-2indicates the OnCE register addresses.

Table 10-2 OnCE Register Addressing

RS4-RS0	Register Selected


00000	OnCE Status and Control Register (OSCR)

00001	Memory Breakpoint Counter (OMBC)

00010	Reserved

00011	Trace Counter (OTC)

00100	Reserved

00101	Reserved

00110	Memory Upper Limit Register (OMULR)

00111	Memory Lower Limit Register (OMLLR)

01000	GDB Register (OGDBR)

01001	PDB Register (OPDBR)

01010	PAB Register for Fetch (OPABFR)

01011	PIL Register (OPILR)

01100	Clear Memory Breakpoint Counter (OMBC)

01101	Reserved

01110	Clear Trace Counter (OTC)

01111	Reserved

10000	Reserved

10001	Program Address Bus FIFO and Increment Counter

10010	Reserved

10011	PAB Register for Decode (OPABDR)

101xx	Reserved

11xx0	Reserved

11x0x	Reserved

110xx	Reserved

11111	No Register Selected

10- 8

ON-CHIP EMULATION (OnCE)

MOTOROLA

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Motorola DSP56000, 24-Bit Digital Signal Processor manual RS4 RS3 RS2 RS1 RS0, OnCE Register Addressing