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24-Bit Digital Signal Processor, DSP56000
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BENCHMARK PROGRAMS
MOTOROLA
BENCHMARK PROGRAMS
B - 17
Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 6 of 8)
Contents
Main
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MOTOROLA TECHNICAL DATA
SEMICONDUCTOR
Addendum to
24-bit Digital Signal Processor Family Manual
DSP56K Family
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TABLE OF CONTENTS
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LIST of FIGURES
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List of Figures (Continued)
LIST of TABLES
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List of Tables (Continued) Table Page
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MAC
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ADDRESS BUSES
2- 4 DSP56K CENTRAL ARCHITECTURE OVERVIEW
Figure 2-1 DSP56K Block Diagram
2.3 ADDRESS BUSES
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OVERVIEW AND DATA ALU ARCHITECTURE
3 - 4 DATA ARITHMETIC LOGIC UNIT
Figure 3-1 DSP56K Block Diagram
24 Bit 56K
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DATA REPRESENTATION AND ROUNDING
Figure 3-10 Convergent Rounding
DATA ARITHMETIC LOGIC UNIT 3 - 15
CAUTION:
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AGU ARCHITECTURE
4 - 4 ADDRESS GENERATION UNIT
Figure 4-1 DSP56K Block Diagram
4.2.2 Offset Register Files (Nn)
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ADDRESSING
Table 4-2 Address Modifier Summary
4 - 18 ADDRESS GENERATION UNIT MOTOROLA
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ADDRESSING
Figure 4-15 Address Modifier Summary
4 - 26 ADDRESS GENERATION UNIT MOTOROLA
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OVERVIEW
5 - 4 PROGRAM CONTROL UNIT
Figure 5-2 DSP56K Block Diagram
24-Bit 56K Mod-
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PROGRAM CONTROL UNIT (PCU) ARCHITECTURE
Figure 5-3 Three-Stage Pipeline
PROGRAM CONTROL UNIT 5 - 7
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INSTRUCTION FORMATS
Figure 6-7 Special Addressing Immediate Data
6 - 16 INSTRUCTION SET INTRODUCTION MOTOROLA
when used to address program memory. This addressing mode is classified as a program reference.
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INSTRUCTION FORMATS
6 - 18 INSTRUCTION SET INTRODUCTION MOTOROLA
Arithmetic Bit Manipulation Move
INSTRUCTION GROUPS
6 - 20 INSTRUCTION SET INTRODUCTION MOTOROLA Figure 6-11 Special Addressing Absolute Short Address
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INSTRUCTION GROUPS
6 - 22 INSTRUCTION SET INTRODUCTION MOTOROLA
Table 6-1 Addressing Modes Summary
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CAUTION
Figure 7-1 Fast and Long Interrupt Examples
RECOGNIZED
(b) DSP56K Long Interrupt
and their IPLs are listed in Table 7-6. For information on on-chip peripheral interrupt pri-
PROCESSING STATES 7 - 13
(a) DSP56K Fast Interrupt
FAST INTERRUPT SERVICE ROUTINE
LONG INTERRUPT SERVICE ROUTINE
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CAUTION
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7 - 20 PROCESSING STATES MOTOROLA
Figure 7-5 Illegal Instruction Interrupt Serviced by a Long Interrupt
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MOTOROLA PROCESSING STATES 7 - 23
Figure 7-7 Trace Exception
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MOTOROLA PROCESSING STATES 7 - 27
Figure 7-8 Fast Interrupt Service Routine
7 - 28 PROCESSING STATES MOTOROLA
i = INTERRUPT ii = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD
Figure 7-9 Two Consecutive Fast Interrupts
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7 - 30 PROCESSING STATES MOTOROLA
Figure 7-10 Long Interrupt Service Routine
MOTOROLA PROCESSING STATES 7 - 31
Figure 7-11 JSR First Instruction of a Fast Interrupt
7 - 32 PROCESSING STATES MOTOROLA
Figure 7-12 JSR Second Instruction of a Fast Interrupt
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RESET PROCESSING STATE
Figure 7-13 Interrupting an REP Instruction
7 - 34 PROCESSING STATES MOTOROLA
RESET PROCESSING STATE
MOTOROLA PROCESSING STATES 7 - 35
i = INTERRUPT ii = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD i% = INTERRUPT REJECTED
Figure 7-14 Interrupting Sequential REP Instructions
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PORT A INTERFACE
8 - 4 PORT A
Figure 8-1 Port A Signals
signals (A0-A15), data bus signals (D0-D15), and bus control. The bus control signals can
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PLL COMPONENTS
9 - 4 PLL CLOCK OSCILLATOR
Figure 9-2 DSP56K Block Diagram
9.2.1 Phase Detector and Charge Pump Loop Filter
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01267891011 345 121314181920212223 151617
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SECTION 11 ADDITIONAL SUPPORT
Dr. BuB Electronic Bulletin Board
ola
Motorola DSP
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SECTION 12
Dr. BuB Electronic Bulletin Board
ola
Motorola DSP
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INSTRUCTION SET DETAILS A - 1
APPENDIX A INSTRUCTION SET DETAILS
Bit Field Manipulation
Loop
Move
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ADDRESSING MODES
A - 12 INSTRUCTION SET DETAILS
Table A-3 DSP56K Addressing Mode Encoding
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ADDRESSING MODES
A - 14 INSTRUCTION SET DETAILS
Table A-4 Addressing Mode Modifier Summary
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CONDITION CODE COMPUTATION
The following notes apply to Table A-5:
MOTOROLA INSTRUCTION SET DETAILS A - 19
Table A-5 Condition Code Computations for Instructions (No Parallel Move)
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ABS
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ADC
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ADD Add ADD
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ADDL
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ADDR
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AND
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ANDI
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ASL
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ASR
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BTST
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CLR
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CMP Compare CMP
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CMPM
DEBUG
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DEBUGcc
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DEC
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ENDDO
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JMP Jump JMP
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JSR
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LSL
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LSR
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LUA
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(S1 2-n)D (no parallel move) MPY (
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NEG
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ORI
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RESET
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ROL
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RTI
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RTS
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STOP
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SUB Subtract SUB
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SUBL
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SUBR
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SWI
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TFR
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WAIT
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B - 4 BENCHMARK PROGRAMS
Table B-1 27-MHz Benchmark Results for the DSP56001R27
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B - 6 BENCHMARK PROGRAMS
Figure B-1 20-Tap FIR Filter Example (Sheet 1 of 2)
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B - 8 BENCHMARK PROGRAMS
Figure B-1 20-Tap FIR Filter Example (Sheet 2 of 2)
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B - 10 BENCHMARK PROGRAMS
Figure B-2 Radix 2, In-Place, Decimation-In-Time FFT (Sheet 1 of 2)
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B - 12 BENCHMARK PROGRAMS
Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 1 of 8)
Figure B-2 Radix 2, In-Place, Decimation-In-Time FFT (Sheet 2 of 2)
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B - 14 BENCHMARK PROGRAMS
Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 3 of 8)
Figure B 3 8 Pole 4 Multiply Cascaded Canonic IIR Filter (Sheet 1 of 2)
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B - 16 BENCHMARK PROGRAMS
Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 5 of 8)
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B - 18 BENCHMARK PROGRAMS
Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 7 of 8)
Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 8 of 8)
BENCHMARK PROGRAMS B - 19
B - 20 BENCHMARK PROGRAMS
BENCHMARK PROGRAMS B - 21
B - 22 BENCHMARK PROGRAMS
BENCHMARK PROGRAMS B - 23
B - 24 BENCHMARK PROGRAMS
BENCHMARK PROGRAMS B - 25
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INDEX
C
B
A
INDEX - 2
G
F
E
D
L
J
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H
INDEX - 4
P
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M
O
R
INDEX - 5