Motorola 24-Bit Digital Signal Processor, DSP56000 manual Address Register Indirect Postdecrement

ADDRESSING

EXAMPLE: MOVE Y0,Y: (R3)-

		BEFORE EXECUTION
		Y1						Y0
47					24	23					0
1	2	3	1	2	3	4	5	6	4	5	6
23					0	23					0
						23	Y MEMORY				0

$4735 X X X X X X

$4734 X X X X X X

150

R3 $4735

150

N3 XXXX

150

M3 $FFFF

Assembler Syntax: (Rn)–

Memory Spaces: P:, X:, Y:, XY:, L:

Additional Instruction Execution Time (Clocks): 0

Additional Effective Address Words: 0

			AFTER EXECUTION
		Y1							Y0
47					24	23						0
1	2	3	1	2	3		4	5	6	4	5	6
23					0	23						0
						23		Y MEMORY				0

$4735	4	5	6	4	5	6
$4734	X	X	X	X	X	X
			15			0
		R3		$4734
			15			0
		N3		XXXX
			15			0
	M3			$FFFF

Figure 4-6 Address Register Indirect — Postdecrement

ify the contents of Rn without an associated data move.

4.4.1.6Indexed By Offset Nn

The address of the operand is the sum of the contents of the address register, Rn, and the contents of the address offset register, Nn (see Table 4-1and Figure 4-9). The con- tents of the Rn and Nn registers are unchanged. This addressing mode, which requires

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