ADDRESSING

EXAMPLE: MOVE X1,X: (R2)+N2

 

BEFORE EXECUTION

 

 

X1

 

X0

47

24

23

0

 

 

 

 

A 5 B 4 C 6

0

0 0 0 0 1

23

0

23

0

 

AFTER EXECUTION

 

 

X1

 

X0

47

24

23

0

 

 

 

A 5 B 4 C 6

0

0 0 0 0 1

23

0

23

0

X MEMORY

230

$3204 X X X X X X

$3200 X X X X X X

150

R2

$3200

150

N2 $0004

150

M2 $FFFF

X MEMORY

 

23

 

 

 

 

 

0

$3204

X

X

X

 

X

X

X

$3200

$

A 5

B

4

C

6

 

 

 

15

 

 

 

0

 

 

R2

 

 

$3204

 

 

 

 

15

 

 

 

0

 

 

N2

 

 

$0004

 

 

 

 

15

 

 

 

0

 

M2

 

 

$FFFF

 

Assembler Syntax: (Rn)+Nn

Memory Spaces: P:, X:, Y:, XY:, L:

Additional Instruction Execution Time (Clocks): 0

Additional Effective Address Words: 0

Figure 4-7 Address Register Indirect — Postincrement by Offset Nn

an extra instruction cycle, cannot be used for making XY: memory references.

4.4.1.7Predecrement By 1

The address of the operand is the contents of the address register, Rn, decremented by 1 before the operand address is used (see Table 4-1and Figure 4-10). The contents of Rn are decremented and stored in the same address register. This addressing mode re- quires an extra instruction cycle. This mode cannot be used for making XY: memory references, nor can it be used for modifying the contents of Rn without an associated data

MOTOROLA

ADDRESS GENERATION UNIT

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Motorola DSP56000, 24-Bit Digital Signal Processor Address Register Indirect Postincrement by Offset Nn, Predecrement By