Motorola 24-Bit Digital Signal Processor, DSP56000 manual Logical Shift Left, Assembler Syntax

INSTRUCTION DESCRIPTIONS

LSL

Logical Shift Left

LSL

4724

Operation: C 0 (parallel move)

Assembler Syntax: LSL D (parallel move)

Description: Logically shift bits 47–24 of the destination operand D one bit to the left and store the result in the destination accumulator. Prior to instruction execution, bit 47 of D is shifted into the carry bit C, and a zero is shifted into bit 24 of the destination accu- mulator D. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected. If a zero shift count is specified, the carry bit is cleared. The difference between LSL and ASL is that LSL operates on only A1 or B1 and always clears the V bit.

Example:

:

LSL B1 #$7F,R0 ;shift B1 one bit to the left, set up R0

:

B

Before Execution

$00:F01234:13579B

B

After Execution

$00:E02468:13579B

SR

$0300

SR

$0309

Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $00:F01234:13579B. The execution of the LSL B instruction shifts the 24-bit value in the B1 register one bit to the left and stores the result back in the B1 register.

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