Motorola 24-Bit Digital Signal Processor, DSP56000 manual Logical Shift Right, Operation

INSTRUCTION DESCRIPTIONS

LSR

Logical Shift Right

LSR

Operation: 0

4724

C (parallel move)

Assembler Syntax: LSR D (parallel move)

Description: Logically shift bits 47–24 of the destination operand D one bit to the right and store the result in the destination accumulator. Prior to instruction execution, bit 24 of D is shifted into the carry bit C, and a zero is shifted into bit 47 of the destination accu- mulator D. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected.

Example:

:

LSR A1 A1,N4 ;shift A1 one bit to the right, set up N4

:

A

Before Execution

$37:444445:828180

A

After Execution

$37:222222:828180

SR

$0300

SR

$0301

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $37:444445:828180. The execution of the LSR A instruction shifts the 24-bit value in the A1 register one bit to the right and stores the result back in the A1 register.

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