Motorola DSP56000, 24-Bit Digital Signal Processor manual Overview and Data ALU Architecture

DATA ARITHMETIC LOGIC UNIT

3.1DATA ARITHMETIC LOGIC UNIT

This section describes the operation of the Data ALU registers and hardware. It dis- cusses data representation, rounding, and saturation arithmetic used within the Data ALU, and concludes with a discussion of the programming model.

3.2OVERVIEW AND DATA ALU ARCHITECTURE

As described in Section 2, The DSP56K family central processing module is composed of three execution units that operate in parallel. They are the Data ALU, address genera- tion unit (AGU), and the program control unit (PCU) (see Figure 3-1). These three units are register oriented rather than bus oriented and interface over the system buses with memory and memory-mapped I/O devices.

The Data ALU (see Figure 3-2) is the first of these execution units to be presented. It bal- ances speed with the capability to process signals that have a wide dynamic range and performs all arithmetic and logical operations on data operands.

The Data ALU registers may be read or written over the XDB and the YDB as 24- or 48- bit operands. The source operands for the Data ALU, which may be 24, 48, or 56 bits, always originate from Data ALU registers. The results of all Data ALU operations are stored in an accumulator.

The 24-bit data words provide 144 dB of dynamic range. This range is sufficient for most real-world applications since the majority of data converters are 16 bits or less – and cer- tainly not greater than 24 bits. The 56-bit accumulator inside the Data ALU provides 336 dB of internal dynamic range so that no loss of precision will occur due to intermediate processing. Special circuitry handles data overflows and roundoff errors.

The Data ALU can perform any of the following operations in a single instruction cycle: multiplication, multiply-accumulate with positive or negative accumulation, convergent rounding, multiply-accumulate with positive or negative accumulation and convergent rounding, addition, subtraction, a divide iteration, a normalization iteration, shifting, and logical operations.

The components of the Data ALU are:

•Four 24-bit input registers

•A parallel, single-cycle, nonpipelined multiply-accumulator/logic unit (MAC)

•Two 48-bit accumulator registers

•Two 8-bit accumulator extension registers

•An accumulator shifter

•Two data bus shifter/limiter circuits

MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 3