Motorola DSP56000, 24-Bit Digital Signal Processor manual List of Figures Number Title

		List of Figures (Continued)
Figure		Page
Number		Title	Number

7-13 Interrupting an REP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 7-14 Interrupting Sequential REP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 7-15 Wait Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 7-16 Simultaneous Wait Instruction and Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 7-17 STOP Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 7-18 STOP Instruction Sequence Followed by IRQA . . . . . . . . . . . . . . . . . . . . . . 7-39 7-19 STOP Instruction Sequence Recovering with RESET . . . . . . . . . . . . . . . . . 7-42

8-1	Port A Signals	8-4
9-1	PLL Block Diagram	9-3
9-2	DSP56K Block Diagram	9-4
9-3	PLL Control Register (PCTL)	9-6
10-1	OnCE Block Diagram	10-3
10-2	DSP56K Block Diagram	10-4
10-3	OnCE Controller and Serial Interface	10-6
10-4	OnCE Command Register	10-7
10-5	OnCE Status and Control Register (OSCR)	10-9
10-6	OnCE Memory Breakpoint Logic	10-12
10-7	OnCE Trace Logic Block Diagram	10-14
10-8	OnCE Pipeline Information and GDB Registers	10-16
10-9	OnCE PAB FIFO	10-17
B-1	20-Tap FIR Filter Example	B-5
B-2	Radix 2, In-Place, Decimation-In-Time FFT	B-7
B-3	8-Pole 4-Multiply Cascaded Canonic IIR Filter	B-9
B-4	LMS FIR Adaptive Filter	B-11
B-5	Real Input FFT Based on Glenn Bergland Algorithm	B-12

MOTOROLA LIST of FIGURES ix