Motorola 24-Bit Digital Signal Processor, DSP56000 MOTOROLA PROCESSING STATES 7 - 31, Figure 7-11 JSR First Instruction of a Fast Interrupt

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
MOTOROLA PROCESSING STATES 7 - 31
JSR
NOT USED
MAIN
PROGRAM
n1
n2
ii2
ii3
ii4
iin
RTI
FAST INTERRUPT
VECTOR LONG INTERRUPT SUBROUTINE
(a) Instruction Fetches from Memory
INTERRUPT CONTROL CYCLE 1 i
INTERRUPT CONTROL CYCLE 2 i
FETCH n1 JSR — ii2 ii3 ii4 iin RTI — n2
DECODE n1 JSR NOP ii2 ii3 ii4 iin RTI NOP n2
EXECUTE n1 JSR NOP ii2 ii3 ii4 iin RTI NOP n2
INSTRUCTION CYCLE COUNT 1 2 3 4 5 6 7 8 9 10 11 12 13
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
INTERRUPTS RE-ENABLED
(b) Program Controller Pipeline
Figure 7-11 JSR First Instruction of a Fast Interrupt
i = INTERRUPT
ii = INTERRUPT INSTRUCTION WORD
n = NORMAL INSTRUCTION WORD