Motorola 24-Bit Digital Signal Processor, DSP56000 Operand Sizes Data Organization in Registers

INSTRUCTION FORMATS

7	0
		BYTE
15	0
		SHORT WORD
23	0
		WORD
47	0
		LONG WORD
55	0

ACCUMULATOR

Figure 6-3 Operand Sizes

6.3.2 Data Organization in Registers

The ten data ALU registers support 8- or 24-bit data operands. Instructions also support 48- or 56-bit data operands by concatenating groups of specific data ALU registers. The eight address registers in the AGU support 16-bit address or data operands. The eight AGU offset registers support 16-bit offsets or may support 16-bit address or data oper- ands. The eight AGU modifier registers support 16-bit modifiers or may support 16-bit address or data operands. The program counter (PC) supports 16-bit address operands. The status register (SR) and operating mode register (OMR) support 8- or 16-bit data operands. Both the loop counter (LC) and loop address (LA) registers support 16-bit address operands.

6.3.2.1Data ALU Registers

The eight main data ALU registers are 24 bits wide. Word operands occupy one register; long-word operands occupy two concatenated registers. The least significant bit (LSB) is the right-most bit (bit 0) and the most significant bit (MSB) is the left-most bit (bit 23 for word operands and bit 47 for long-word operands). The two accumulator extension regis- ters are eight bits wide.

When an accumulator extension register acts as a source operand, it occupies the low- order portion (bits 0–7) of the word and the high-order portion (bits 8–23) is sign extended (see Figure 6-4). When used as a destination operand, this register receives the low-order portion of the word, and the high-order portion is not used. Accumulator operands occupy an entire group of three registers (i.e., A2:A1:A0 or B2:B1:B0). The LSB is the right-most bit (bit 0), and the MSB is the left-most bit (bit 55).

6 - 6 INSTRUCTION SET INTRODUCTION MOTOROLA