Motorola 24-Bit Digital Signal Processor, DSP56000 Negate Accumulator, Operation Assembler Syntax

INSTRUCTION DESCRIPTIONS

	NEG	Negate Accumulator	NEG
Operation:		Assembler Syntax:
	0–D ➞ D (parallel move)	NEG	D (parallel move)

Description: Negate the destination operand D and store the result in the destination accumulator. This is a 56-bit, twos-complement operation.

Example:

:

NEG B X1,X:(R3)+ Y:(R6)–,A

:

Before Execution

B $00:123456:789ABC

;0–B ➞ B, update A,X1,R3,R6

After Execution

B$FF:EDCBA9:876544

Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $00:123456:789ABC. The NEG B instruction takes the twos complement of the value in the B accumulator and stores the 56-bit result back in the B accumulator.

Condition Codes:

15	14	13	12	11		10	9		8	7	6	5	4	3		2	1		0
LF	DM	T	**		S1	S0		I1	I0	S	L	E	U		N	Z		V	C
				MR										CCR

S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if limiting (parallel move) or overflow has occurred in result

E — Set if the signed integer portion of A or B result is in use

U — Set if A or B result is unnormalized

N — Set if bit 55 of A or B result is set

Z — Set if A or B result equals zero

V — Set if overflow has occurred in A or B result

Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 CONDITION CODE COMPUTATION for complete details.

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