Motorola 24-Bit Digital Signal Processor, DSP56000 manual Instruction Fields S1∗S2 Q Q Q Sign k

INSTRUCTION DESCRIPTIONS

MPYR	Signed Multiply and Round
Instruction Fields 1:
S1∗S2 Q Q Q	Sign k	D d

MPYR

X0 X0	0	0	0	+	0	A	0
Y0 Y0	0	0	1	–	1	B	1
X1 X0	0	1	0
Y1 Y0	0	1	1
X0 Y1	1	0	0
Y0 X0	1	0	1
X1 Y0	1	1	0
Y1 X1	1	1	1

Note: Only the indicated S1∗S2 combinations are valid. X1∗X1 and Y1∗Y1 are not valid.

Timing: 2+mv oscillator clock cycles

Memory: 1+mv program words

Example 2:

:
MPYR -Y1,		#14, B
:
			Before Execution
	Y1
		$654321

;

Y1

After Execution

$654321

B

$00:000000:000000

B

$FF:FFFE6B:000000

Explanation of Example 2: The content of Y1 is negated, multiplied by 2-14, rounded to a single precision number (24 bits in B1) and placed in the B accumulator. The net effect of this operation is negate the content of Y1 and divide the result by 214, place the result in the accumulator and then round to a single precision number. An alternate interpreta- tion is that X1 is negated and placed in the accumulator, right shifted 14 places, filled with the sign bit (0 for a positive number and 1 for a negative number) and then rounded to a single precision number.

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