STOP PROCESSING STATE

IRQA

FETCH

n3

n4

 

 

 

 

ii1

 

 

 

 

 

 

 

 

 

 

DECODE

n2

STOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXECUTE

n1

n2

STOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STOP CYCLE COUNT

1

2

3

4

5

6

7

8

(9)

 

 

 

 

 

 

 

 

 

 

CLOCK STOPPED

IRQA = INTERRUPT REQUEST A SIGNAL

n= NORMAL INSTRUCTION WORD STOP = INTERRUPT INSTRUCTION WORD

RESUME STOP CYCLE COUNT 4,

INTERRUPTS ENABLED

131,072 T OR 16 T CYCLE COUNT STARTED

Figure 7-18 STOP Instruction Sequence Followed by IRQA

Figure 7-18shows the system being restarted by asserting the IRQA signal. If the exit from stop state was caused by a low level on the IRQA pin, then the processor will ser- vice the highest priority pending interrupt. If no interrupt is pending, then the processor resumes at the instruction following the STOP instruction that brought the processor into the stop state.

An IRQA deasserted before the end of the stop cycle count will not be recognized as pending. If IRQA is asserted when the stop cycle count completes, then an IRQA inter- rupt will be recognized as pending and will be arbitrated with any other interrupts.

Specifically, when IRQA is asserted, the internal clock generator is started and begins a delay determined by the SD bit of the OMR. When the chip uses the internal clock oscil- lator, the SD bit should be set to zero, to allow a longer delay time of 128K T cycles (131,072 T cycles) so that the clock oscillator may stabilize. When the chip uses a stable external clock, the SD bit may be set to one to allow a shorter (16 T cycle) delay time and a faster start up of the chip.

For example, assume that SD=0 so that the 128K T counter is used. During the 128K T count, the processor ignores interrupts until the last few counts and, at that time, begins to synchronize them. At the end of the 128K T cycle delay period, the chip restarts instruction processing, completes stop cycle 4 (interrupt arbitration occurs at this time), and executes stop cycles 5, 6, 7, and 8 (it takes 17T from the end of the 128K T delay to

MOTOROLA

PROCESSING STATES

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Motorola DSP56000, 24-Bit Digital Signal Processor manual Stop Instruction Sequence Followed by Irqa