Motorola 24-Bit Digital Signal Processor manual PLL Clock Oscillator Introduction PLL Components

SECTION CONTENTS

SECTION 9.1 PLL CLOCK OSCILLATOR INTRODUCTION	3
SECTION 9.2 PLL COMPONENTS	3
9.2.1 Phase Detector and Charge Pump Loop Filter	4
9.2.2 Voltage Controlled Oscillator (VCO)	5
9.2.3 Frequency Multiplier	5
9.2.4 Low Power Divider (LPD)	5
9.2.5 PLL Control Register (PCTL)	5
9.2.5.1 PCTL Multiplication Factor Bits (MF0-MF11) - Bits 0-11	5
9.2.5.2 PCTL Division Factor Bits (DF0-DF3) - Bits 12-15	6
9.2.5.3 PCTL XTAL Disable Bit (XTLD) - Bit 16	7
9.2.5.4 PCTL STOP Processing State Bit (PSTP) - Bit 17	7
9.2.5.5 PCTL PLL Enable Bit (PEN) - Bit 18	8
9.2.5.6 PCTL Clock Output Disable Bits (COD0-COD1) - Bits 19-20 .... 8
9.2.5.7 PCTL Chip Clock Source Bit (CSRC) - Bit 21	9
9.2.5.8 PCTL CKOUT Clock Source Bit (CKOS) - Bit 22	9
9.2.5.9 PCTL Reserved Bit - Bit 23	9
SECTION 9.3 PLL PINS	9
SECTION 9.4 PLL OPERATION CONSIDERATIONS	11
9.4.1 Operating Frequency	11
9.4.2 Hardware Reset	11
9.4.3 Operation with PLL Disabled	12
9.4.4 Changing the MF0-MF11 Bits	12
9.4.5 Change of DF0-DF3 Bits	13
9.4.6 Loss of Lock	13
9.4.7 STOP Processing State	13
9.4.8 CKOUT Considerations	14
9.4.9 Synchronization Among EXTAL, CKOUT, and the Internal Clock	14

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