Motorola 24-Bit Digital Signal Processor, DSP56000 manual List of Figures Number Title, Viii

		List of Figures (Continued)
Figure		Page
Number		Title	Number

4-14 Bit-Reverse Address Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4-15 Address Modifier Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

5-1	Program Address Generator	5-3
5-2	DSP56K Block Diagram	5-4
5-3	Three-Stage Pipeline	5-7
5-4	Program Control Unit Programming Model	5-8
5-5	Status Register Format	5-9
5-6	OMR Format	5-14
5-7	Stack Pointer Register Format	5-15
5-8	SP Register Values	5-15
5-9	DSP56K Central Processing Module Programming Model	5-18
6-1	DSP56K Central Processing Module Programming Model	6-4
6-2	General Format of an Instruction Operation Word	6-5
6-3	Operand Sizes	6-6
6-4	Reading and Writing the ALU Extension Registers	6-7
6-5	Reading and Writing the Address ALU Registers	6-7
6-6	Reading and Writing Control Registers	6-8
6-7	Special Addressing – Immediate Data	6-15
6-8	Special Addressing – Absolute Addressing	6-16
6-9	Special Addressing – Immediate Short Data	6-17
6-10	Special Addressing – Short Jump Address	6-18
6-11	Special Addressing – Absolute Short Address	6-19
6-12	Special Addressing – I/O Short Address	6-20
6-13	Hardware DO Loop	6-25
6-14	Nested DO Loops	6-26
6-15	Classifications of Parallel Data Moves	6-27
6-16	Parallel Move Examples	6-28
7-1	Fast and Long Interrupt Examples	7-13
7-2	Interrupt Priority Register (Addr X:$FFFF)	7-14
7-3	Interrupting an SWI	7-18
7-4	Illegal Instruction Interrupt Serviced by a Fast Interrupt	7-19
7-5	Illegal Instruction Interrupt Serviced by a Long Interrupt	7-20
7-6	Repeated Illegal Instruction	7-21
7-7	Trace Exception	7-23
7-8	Fast Interrupt Service Routine	7-27
7-9	Two Consecutive Fast Interrupts	7-28
7-10	Long Interrupt Service Routine	7-30
7-11	JSR First Instruction of a Fast Interrupt	7-31
7-12	JSR Second Instruction of a Fast Interrupt	7-32

viii LIST of FIGURES MOTOROLA