Motorola 24-Bit Digital Signal Processor, DSP56000 manual Shift Right and Add Accumulators

INSTRUCTION DESCRIPTIONS

	ADDR	Shift Right and Add Accumulators		ADDR
Operation:			Assembler Syntax:
	S+D / 2➞D (parallel move)		ADDR S,D (parallel move)

Description: Add the source operand S to one-half the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the right while the MS bit of D is held constant prior to the addition oper- ation. In contrast to the ADDL instruction, the carry bit is always set correctly, and the overflow bit can only be set by the addition operation and not by an overflow due to the initial shifting operation. This instruction is useful for efficient divide and decimation in time (DIT) FFT algorithms.

Example:

:

ADDR B,A X0,X:(R1)+N1 Y0,Y:(R4)– ;B+A / 2➞A, save X0 and Y0

:

A

Before Execution

$80:000000:2468AC

A

After Execution

$C0:013570:123456

B

$00:013570:000000

B

$00:013570:000000

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $80:000000:2468AC, and the 56-bit B accumulator contains the value $00:013570:000000. The ADDR B,A instruction adds one-half the value in the A accu- mulator to the value in the B accumulator and stores the 56-bit result in the A accumula- tor.

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