Motorola 24-Bit Digital Signal Processor Address A0-A15, Data D0-D23, Port a Bus Control Signals

PORT A INTERFACE

8.2.2.1Address (A0–A15)

These three-state output pins specify the address for external program and data memory accesses. To minimize power dissipation, A0–A15 do not change state when external memory spaces are not being accessed.

8.2.2.2Data (D0–D23)

These pins provide the bidirectional data bus for external program and data memory ac- cesses. D0–D23 are in the high-impedance state when the bus grant signal is asserted.

8.2.3Port A Bus Control Signals

The following paragraphs describe the Port A bus control signals. The bus control signals provide the means to connect additional bus masters (which may be additional DSPs, mi- croprocessors, direct memory access (DMA) controllers, etc.) to the port A bus. They are three-stated during reset and may require pullup resistors to prevent erroneous operation.

8.2.3.1Read Enable (RD)

This three-state output is asserted to read external memory on the data bus (D0–D23).

8.2.3.2Write Enable (WR)

This three-state output is asserted to write external memory on the data bus (D0–D23).

8.2.3.3Port A Access Control Signals

Port A features a group of configurable pins that perform bus arbitration and bus access control. The pins, such as Bus Needed (BN), Bus Request. (BR), Bus Grant (BG), Bus Wait (WT), and Bus Strobe (BS), and their designations differ between members of the DSP56K family and are explained in the respective devices’ user manuals.

8.2.4Interrupt and Mode Control

Port A features a pin set that selects the chip’s operating mode and receives interrupt re- quests from external sources. The pins and their designations vary between members of the DSP56K family and are explained in the respective devices’ user manuals.

8.2.5 Port A Wait States

The DSP56K processor features two methods to allow the user to accommodate slow memory by changing the port A bus timing. The first method uses the16-bit bus control register (BCR), which resides in X Data memory space. The BCR allows a fixed number of wait states to be inserted in a given memory access to all locations in any one of the four memory spaces: X, Y, P, and I/O. The second method uses the bus strobe/wait (BS/

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