Motorola 24-Bit Digital Signal Processor, DSP56000 manual Divide Interation, Div S,D, Description

INSTRUCTION DESCRIPTIONS

DIV			Divide Interation
Operation: If D[55]⊕S[23]=1,
55	47	23	0

DIV

then C+S D

Destination Accumulator D

55 47 23 0

else

Destination Accumulator D where ⊕ denotes the logical exclusive OR operator

C–S D

Assembler Syntax: DIV S,D

Description:

Divide the destination operand D by the source operand S and store the result in the destination accumulator D. The 48-bit dividend must be a positive fraction which has been sign extended to 56-bits and is stored in the full 56-bit destination accumula- tor D. The 24-bit divisor is a signed fraction and is stored in the source operand S.

Each DIV iteration calculates one quotient bit using a nonrestoring fractional division algorithm (see description on the next page). After the execution of the first DIV instruc- tion, the destination operand holds both the partial remainder and the formed quotient. The partial remainder occupies the high-order portion of the destination accumulator D and is a signed fraction. The formed quotient occupies the low-order portion of the desti- nation accumulator D (A0 or B0) and is a positive fraction. One bit of the formed quotient is shifted into the LS bit of the destination accumulator at the start of each DIV iteration. The formed quotient is the true quotient if the true quotient is positive. If the true quotient is negative, the formed quotient must be negated. Valid results are obtained only when D < S and the operands are interpreted as fractions. Note that this condition ensures that the magnitude of the quotient is less than one (i.e., is fractional) and pre- cludes division by zero.

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