Motorola 24-Bit Digital Signal Processor, DSP56000 manual PHASE-LOCKED Loop PLL Based Clocking

SECTION CONTENTS

SECTION 2.1 DSP56K CENTRAL ARCHITECTURE OVERVIEW	3
SECTION 2.2 DATA BUSES	3
SECTION 2.3 ADDRESS BUSES	4
SECTION 2.4 DATA ALU	5
SECTION 2.5 ADDRESS GENERATION UNIT	5
SECTION 2.6 PROGRAM CONTROL UNIT	5
SECTION 2.7 MEMORY EXPANSION PORT (PORT A)	6
SECTION 2.8 ON-CHIP EMULATOR (OnCE)	6
SECTION 2.9 PHASE-LOCKED LOOP (PLL) BASED CLOCKING	6

2 - 2 DSP56K CENTRAL ARCHITECTURE OVERVIEW MOTOROLA