Motorola 24-Bit Digital Signal Processor, DSP56000 manual Pctl Division Factor Bits DF0-DF3 Bits

PLL COMPONENTS

11 10 9 8 7 6 5 4 3 2 1 0

MF11 MF10 MF9 MF8

MF7 MF6 MF5 MF4 MF3

MF2 MF1 MF0

23 22 21 20 19 18 17 16 15 14 13 12

**

CKOS CSRC COD1 COD0 PEN PSTP XTLD

DF3

DF2

DF1

DF0

**Reserved bits, read as zero, should be written with zero for future compatibility.

Figure 9-3 PLL Control Register (PCTL)

shows how to program the MF0-MF11 bits. The VCO will oscillate at a frequency of MF x Fext, where Fext is the EXTAL clock frequency. The multiplication factor must be chosen to ensure that the resulting VCO output frequency will lay in the range specified in the device’s Technical Data Sheet. Any time a new value is written into the MF0-MF11 bits, the PLL will lose the lock condition. After a time delay, the PLL will relock. The MF0-MF11 bits are set to a pre-determined value during hardware reset; the value is implementation dependent and may be found in each DSP56K family member’s user manual.

Table 9-1 Multiplication Factor Bits MF0-MF11

MF11-MF0	Multiplication
	Factor MF
$000	1
$001	2
$002	3
•	•
•	•
$FFE	4095
$FFF	4096

9.2.5.2 PCTL Division Factor Bits (DF0-DF3) - Bits 12-15

The Division Factor Bits DF0-DF3 define the divide factor (DF) of the low power divider. These bits specify any power of two divide factor in the range from 20 to 215. Table 9-2

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