PLL COMPONENTS
9 - 6 PLL CLOCK OSCILLATOR
MOTOROLA
shows how to program the MF0-MF11 bits. The VCO will oscillate at a frequency of
MF x F
ext
, where F
ext
is the EXTAL clock frequency. The multiplication factor must be
chosen to ensure that the resulting VCO output frequency will lay in the range specified
in the device’s Technical Data Sheet. Any time a new value is written into the MF0-MF11
bits, the PLL will lose the lock condition. After a time delay, the PLL will relock. The
MF0-MF11 bits are set to a pre-determined value during hardware reset; the value is
implementation dependent and may be found in each DSP56K family member’s user
manual.
Table 9-1 Multiplication Factor Bits MF0-MF11
9.2.5.2 PCTL Division Factor Bits (DF0-DF3) - Bits 12-15
The Division Factor Bits DF0-DF3 define the divide factor (DF) of the low power divider.
These bits specify any power of two divide factor in the range from 2
0
to 2
15
. Table 9-2
MF11-MF0 Multiplication
Factor MF
$000 1
$001 2
$002 3
••
••
$FFE 4095
$FFF 4096
01267891011 345121314181920212223 151617
MF0MF1MF2MF3MF4MF5MF6MF7MF8MF9MF10MF11
DF0DF1DF2DF3XTLDPSTPPENCSRCCKOS** COD0
** Reserved bits, read as zero, should be written with zero for future compatibility.
COD1
Figure 9-3 PLL Control Register (PCTL)