Motorola DSP56000 manual Appendix a Instruction SET Details, Operand Sizes

INSTRUCTION FORMATS

shown in Figure 6-2.Most instructions specify data movement on the XDB, YDB, and data ALU operations in the same operation word. The DSP56K performs each of these oper- ations in parallel.

23 8 7 0

OPCODE

DATA BUS MOVEMENT

X X X X X X X X

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Figure 6-2 General Format of an Instruction Operation Word

The data bus movement field provides the operand reference type. It selects the type of memory or register reference to be made, the direction of transfer, and the effective address(es) for data movement on the XDB and YDB. This field may require additional information to fully specify the operand for certain addressing modes. An effective address extension word following the operation word provides an immediate data address or an absolute address if required (see Section 6.3.5.3 for the description of special addressing modes). Examples of operations that may include the extension word include the move operations X:, X:R, Y:, R:Y, and L:. Additional information is presented in

APPENDIX A - INSTRUCTION SET DETAILS.

The opcode field of the operation word specifies the data ALU operation or the program control unit operation to be performed, and any additional operands required by the instruction. Only those data ALU and program control unit operations that can accompany data bus movement will be specified in the opcode field of the instruction. Other data ALU, program control unit, and all address ALU operations will be specified in an instruction word with a different format. These formats include operation words which contain short immediate data or short absolute addresses (see Section 6.3.5.3 for the description of special addressing modes).

6.3.1 Operand Sizes

Operand sizes are defined as follows: a byte is 8 bits long, a short word is16 bits long, a word is 24 bits long, a long word is 48 bits long, and an accumulator is 56 bits long (see Figure 6-3). The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Implicit instructions support some subset of the five sizes shown in Figure 6-3.

MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 5