CONDITION CODE COMPUTATION
MOTOROLA
INSTRUCTION SET DETAILS A - 15
A.5 CONDITION CODE COMPUTATION
The condition code register (CCR) portion of the status register (SR) consists of eight
defined bits:
S — Scaling Bit N — Negative Bit
L — Limit Bit Z — Zero Bit
E — Extension Bit V — Overflow Bit
U — Unnormalized Bit C — Carry Bit
The E, U, N, Z, V, and C bits are
true
condition code bits that reflect the condition of the
result of a data ALU operation
. These condition code bits are not latched and are not
affected by address ALU calculations or by data transfers over the X, Y, or global
data buses. The L bit is a latching overflow bit which indicates that an overflow has
occurred in the data ALU or that data limiting has occurred when moving the contents of
the A and/or B accumulators. The S bit is a latching bit used in block floating point oper-
ations to indicate the need to scale the number in A or B. See SECTION 5 – PROGRAM
CONTROL UNIT for information on the MR portion of the status register.
The standard definition of the condition code bits follows. Exceptions to these stan-
dard definitions are given in the notes which follow Table A-5.
MR CCR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LF DM T ** S1 S0 I1 I0 S L E U N Z V C