Motorola DSP56000 manual Methods of Entering the Debug Mode, External Debug Request During Reset

METHODS OF ENTERING THE DEBUG MODE

10.6METHODS OF ENTERING THE DEBUG MODE

The chip acknowledges having entered the debug mode by pulsing low the DSO line, in- forming the external command controller that the chip has entered the debug mode and is waiting for commands.The following paragraphs discuss conditions that bring the pro- cessor into the debug mode.

10.6.1 External Debug Request During RESET

Holding the DR line asserted during the assertion of RESET causes the chip to enter the debug mode. After receiving the acknowledge, the external command controller must deassert the DR line before sending the first command. Note that in this case the chip does not execute any instruction before entering the debug mode.

10.6.2 External Debug Request During Normal Activity

Holding the DR line asserted during normal chip activity causes the chip to finish the ex- ecution of the current instruction and then enter the debug mode. After receiving the ac- knowledge, the external command controller must deassert the DR line before sending the first command. Note that in this case the chip completes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. This process is the same for any newly fetched instruction including instructions fetched by the interrupt processing, or those that will be aborted by the interrupt processing.

10.6.3 External Debug Request During STOP

Asserting DR when the chip is in the stop state (i. e., has executed a STOP instruction) and keeping it asserted until an acknowledge pulse in DSO is produced causes the chip to exit the stop state and enter the debug mode. After receiving the acknowledge, the ex- ternal command controller must deassert DR before sending the first command. Note that in this case, the chip completes the execution of the STOP instruction and halts after the next instruction enters the instruction latch.

10.6.4 External Debug Request During WAIT

Asserting DR when the chip is in the wait state (i. e., has executed a WAIT instruction) and keeping it asserted until an acknowledge pulse in DSO is produced causes the chip to exit the wait state and enter the debug mode. After receiving the acknowledge, the ex- ternal command controller must deassert DR before sending the first command. Note that in this case, the chip completes the execution of the WAIT instruction and halts after the next instruction enters the instruction latch.

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