NORMAL PROCESSING STATE
7 - 6 PROCESSING STATES
MOTOROLA
second instruction of the downloaded code at P:$0001 of the internal RAM. However, the
ANDI instruction allows the OMR to be changed before the JMP instruction uses it, and
the JMP fetches P:$0000 of the internal RAM.
Case 4:
An interrupt has two additional control cycles that are executed in the interrupt
controller concurrently with the fetch, decode, and execute cycles (see Section 7.3 and
Figure 7-4). During these two control cycles, the interrupt is arbitrated by comparing the
interrupt mask level with the interrupt priority level (IPL) of the interrupt and allowing or
disallowing the interrupt. Therefore, if the interrupt mask is changed after an interrupt is
arbitrated and accepted as pending but before the interrupt is executed, the interrupt will
be executed, regardless of what the mask was changed to. The following examples show
that the old interrupt mask is in effect for up to four additional instruction cycles after the
interrupt mask is changed. All instructions shown in the examples here are one-word in-
structions; however, one two-word instruction can replace two one-word instructions
except where noted.
1. Program flow with no interrupts after interrupts are disabled:
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ORI #03,MR ;Disable interrupts
INST 1
INST 2
INST 3
INST 4
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2. The four possible variations in program flow that may occur after interrupts are
disabled:
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ORI #03,MR ORI #03,MR ORI #03,MR ORI #03,MR
II (See Note 2) INST 1 INST 1 INST 1
II+1 II INST 2 INST 2
INST 1 II+1 ll INST 3 (See Note 1)
INST 2 INST 2 II+1 ll
INST 3 INST 3 INST 3 II+1
INST 4 INST 4 INST 4 INST 4
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