Motorola DSP56000 Voltage Controlled Oscillator VCO, Frequency Multiplier, Low Power Divider LPD

PLL COMPONENTS

The charge pump loop filter receives signals from the PD, and either increases or decreases the phase based on the PD signals. An external capacitor is connected to the PCAP pin (described in Section 9.3) and determines the PLL operation. (See the appro- priate Technical Data Sheet for more detailed information about a particular device’s phase and frequency.)

After the PLL locks on to the proper phase/frequency, it reverts to the narrow bandwidth mode, which is useful for tracking small changes due to frequency drift of the EXTAL clock.

9.2.2Voltage Controlled Oscillator (VCO)

The VCO can oscillate at frequencies from the minimum speed specified in a device’s Technical Data Sheet (typically10 MHz) up to the device’s maximum allowed clock input frequency.

9.2.3Frequency Multiplier

Inside the PLL, the frequency multiplier divides the VCO output frequency by its division factor (n). If the frequency multiplier’s output frequency is different from the EXTAL fre- quency, the charge pump loop filter generates an error signal. The error signal causes the VCO to adjust its frequency until the two input signals to the phase detector have the same phase and frequency. At this point (phase lock) the VCO will be running at n times the EXTAL frequency, where n is the multiplication factor for the frequency multiplier. The programmable multiplication factor ranges from 1 to 4096

9.2.4Low Power Divider (LPD)

The Low Power Divider (LPD) divides the output frequency of the VCO by any power of 2 from 20 to 215. Since the LPD is not in the closed loop of the PLL, changes in the divide factor will not cause a loss of lock condition. This fact is particularly useful for utilizing the LPD in low power consumption modes when the chip is not involved in intensive calcula- tions. This can result in significant power saving. When the chip is required to exit the low power mode, it can immediately do so with no time needed for clock recovery or PLL lock.

9.2.5PLL Control Register (PCTL)

The PLL control register (PCTL) is a 24-bit read/write register which directs the operation of the on-chip PLL. It is mapped into the processor’s internal X memory at X:$FFFD. The PCTL control bits are described in the following sections.

9.2.5.1PCTL Multiplication Factor Bits (MF0-MF11) - Bits 0-11

The Multiplication Factor Bits MF0-MF11 define the multiplication factor (MF) that will be applied to the PLL input frequency. The MF can be any integer from 1 to 4096. Table 9-1

MOTOROLA PLL CLOCK OSCILLATOR 9 - 5