ON-CHIP EMULATION (OnCE) PINS
10- 6 ON-CHIP EMULATION (OnCE)
MOTOROLA
10.2.2 Debug Serial Clock/Chip Status 1 (DSCK/OS1)
The DSCK/OS1 pin supplies the serial clock to the OnCE when it is an input. The serial
clock provides pulses required to shift data into and out of the OnCE serial port. (Data is
clocked into the OnCE on the falling edge and is clocked out of the OnCE serial port on
the rising edge.) The debug serial clock frequency must be no greater than 1/8 of the pro-
cessor clock frequency. When an output, this pin, in conjunction with the OS0 pin,
provides information about the chip status (see Table 10-1). The DSCK/OS1 pin is an out-
put when the chip is not in debug mode. When switching from output to input, the pin is
three-stated. During hardware reset, this pin is defined as an output and it is driven low.
Note:
To avoid possible glitches, an external pull-down resistor should be attached to this
pin.
10.2.3 Debug Serial Output (DSO)
Serial data is read from the OnCE through the DSO pin, as specified by the last command
received from the external command controller. Data is always shifted out the OnCE serial
port most significant bit (MSB) first. Data is clocked out of the OnCE serial port on the ris-
ing edge of DSCK.
The DSO pin also provides acknowledge pulses to the external command controller.
When the chip enters the debug mode, the DSO pin will be pulsed low to indicate (ac-
knowledge) that the OnCE is waiting for commands. After receiving a read command, the
DSO pin will be pulsed low to indicate that the requested data is available and the OnCE
serial port is ready to receive clocks in order to deliver the data. After receiving a write
command, the DSO pin will be pulsed low to indicate that the OnCE serial port is ready to
receive the data to be written; after the data is written, another acknowledge pulse will be
provided.
During hardware reset and when the processor is idle, the DSO pin is held high.
Table 10-1 Chip Status Information
OS1 OS0 Status
0 0 Normal State
0 1 Stop or Wait State
1 0 Chip waits for bus mastership
1 1 Chip waits for end of memory wait states
(due to WT assertion or BCR)