INSTRUCTION DESCRIPTIONS
A - 32 INSTRUCTION SET DETAILS MOTOROLA
Operation: Assembler Syntax:
S • D[47:24]➞D[47:24] (parallel move) AND S,D (parallel move)
where •denotes the logical AND operator
Description: Logically AND the source operand S with bits 47–24 of the destination
operand D and store the result in bits 47–24 of the destination accumulator. This instruc-
tion is a 24-bit operation. The remaining bits of the destination operand D are not
affected.
Example: :
AND X0,A1 (R5)–N5 ;AND X0 with A1, update R5 using N5
:
Explanation of Example: Prior to execution, the 24-bit X0 register contains the value
$FF0000, and the 56-bit A accumulator contains the value $00:123456:789ABC. The
AND X0,A instruction logically ANDs the 24-bit value in the X0 register with bits 47–24 of
the A accumulator (A1) and stores the result in the A accumulator with bits 55–48 and
23–0 unchanged.
Condition Codes:
S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION
L — Set if limiting occurs during parallel move
N — Set if bit 47 of A or B result is set
Z— Set if bits 47–24 of A or B result are zero
V — Always cleared
AND Logical AND AND
Before Execution After Execution
X0 X0
$FF0000
A A
$00:123456:789ABC $00:120000:789ABC
$FF0000
MR CCR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LF DM T ** S1 S0 I1 I0 SLEU NZ VC