Motorola 24-Bit Digital Signal Processor, DSP56000 manual Signed Multiply-Accumulate and Round

INSTRUCTION DESCRIPTIONS

	MACR	Signed Multiply-Accumulate and Round			MACR
Operation:			Assembler Syntax:
	D±S1∗S2+r➞D (parallel move)		MACR	(±)S1,S2,D (parallel move)
	D±S1∗S2+r➞ D (parallel move)		MACR	(±)S2,S1,D (parallel move)
	D±(S1∗2-n)+r➞D (no parallel move)		MACR	(±)S,#n,D (no parallel move)

Description: Multiply the two signed 24-bit source operands S1 and S2 (or the signed 24-bit source operand S by the positive 24-bit immediate operand 2-n), add/subtract the product to/from the specified 56-bit destination accumulator D, and then round the result using convergent rounding. The rounded result is stored in the destination accumulator D.

The “–” sign option negates the specified product prior to accumulation. The default sign option is “+”.

The contribution of the LS bits of the result is rounded into the upper portion of the desti- nation accumulator (A1 or B1) by adding a constant to the LS bits of the lower portion of the accumulator (A0 or B0). The value of the constant added is determined by the scal- ing mode bits S0 and S1 in the status register. Once rounding has been completed, the LS bits of the destination accumulator D (A0 or B0) are loaded with zeros to maintain an unbiased accumulator value which may be reused by the next instruction. The upper por- tion of the accumulator (A1 or B1) contains the rounded result which may be read out to the data buses. Refer to the RND instruction for more complete information on the con- vergent rounding process.

Example 1:
:	;X0∗Y0+B➞B, and B, update X0,Y0,R4
MACR X0,Y0,B B,X0 Y:(R4)+N4,Y0
:

X0

Before Execution

$123456

X0

After Execution

$100000

Y0

$123456

Y0

$987654

B

$00:100000:000000

B

$00:1296CE:000000

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