Motorola 24-Bit Digital Signal Processor, DSP56000 Table A-3 DSP56K Addressing Mode Encoding, M a

ADDRESSING MODES

Table A-3 DSP56K Addressing Mode Encoding

Addressing Mode

Mode

MMM

Reg

RRR

Addressing Categories

U P M A

Assembler

Syntax

		Register Direct
Data or Control Register	—		—				X	(See Table A-1)
Address Register	—		—				X	Rn
Address Offset Register	—		—				X	Nn
Address Modifier Register	—		—				X	Mn
	Address Register Indirect
No Update	100		Rn		X	X	X	(Rn)
Postincrement by 1	011		Rn	X	X	X	X	(Rn) +
Postdecrement by 1	010		Rn	X	X	X	X	(Rn) -
Postincrement by Offset Nn	001		Rn	X	X	X	X	(Rn) + Nn
Postdecrement by Offset Nn	000		Rn	X		X	X	(RN) - Nn
Indexed by Offset Nn	101		Rn			X	X	(Rn + Nn)
Predecrement by 1	111		Rn			X	X	- (Rn)
			Special
Immediate Data	110		100			X		#xxxxxx
Absolute Address	110		000			X	X	xxxx
Immediate Short Data	—		—					#xx
Short Jump Address	—		—				X	xxx
Absolute Short Address	—		—				X	aa
I/O Short Address	—		—				X	pp
Implicit	—		—				X

Update Mode (U)	– Modifies address registers without any associated data move.
Parallel Mode (P)	– Used in instructions where two effective addresses are required.
Memory Mode (M)	– Refers to operands in memory using an effective addressing field.
Alterable Mode (A)	– Refers to alterable or writable registers or memory.

A - 12 INSTRUCTION SET DETAILS MOTOROLA