SUMMARY OF DSP56K FAMILY FEATURES
1- 10 DSP56K FAMILY INTRODUCTION
MOTOROLA
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Precision
— The data paths are 24 bits wide, providing 144 dB of dynamic range;
intermediate results held in the 56-bit accumulators can range over 336 dB.
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Parallelism
— Each on-chip execution unit (AGU, program control unit, data ALU),
memory, and peripheral operates independently and in parallel with the other units
through a sophisticated bus system. The data ALU, AGU, and program control unit
operate in parallel so that an instruction prefetch, a 24-bit x 24-bit multiplication, a 56-
bit addition, two data moves, and two address-pointer updates using one of three
types of arithmetic (linear, modulo, or reverse-carry) can be executed in a single
instruction cycle. This parallelism allows a four-coefficient IIR filter section to be
executed in only four cycles, the theoretical minimum for single-multiplier architecture.
At the same time, the two serial controllers can send and receive full-duplex data, and
the host port can send/receive simplex data.
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Flexibility
— While many other DSPs need external communications circuitry to
interface with peripheral circuits (such as A/D converters, D/A converters, or host
processors), the DSP56K family provides on-chip serial and parallel interfaces which
can support various configurations of memory and peripheral modules
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Sophisticated Debugging
— Motorola’s on-chip emulation technology (OnCE) allows
simple, inexpensive, and speed independent access to the internal registers for
debugging. OnCE tells application programmers exactly what the status is within the
registers, memory locations, buses, and even the last five instructions that were
executed.
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Phase-locked Loop (PLL) Based Clocking
— PLL allows the chip to use almost any
available external system clock for full-speed operation while also supplying an output
clock synchronized to a synthesized internal core clock. It improves the synchronous
timing of the processors’ external memory port, eliminating the timing skew common
on other processors.
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Invisible Pipeline
— The three-stage instruction pipeline is essentially invisible to the
programmer, allowing straightforward program development in either assembly
language or a high-level language such as a full Kernighan and Ritchie C.
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Instruction Set
— The instruction mnemonics are MCU-like, making the transition
from programming microprocessors to programming the chip as easy as possible. The
orthogonal syntax controls the parallel execution units. The hardware DO loop
instruction and the repeat (REP) instruction make writing straight-line code obsolete.