Motorola 24-Bit Digital Signal Processor manual Pipeline Information and Global Data BUS Register

PIPELINE INFORMATION AND GLOBAL DATA BUS REGISTER

10.6.5 Software Request During Normal Activity

Upon executing the DEBUG or DEBUGcc instruction when the specified condition is true, the chip enters the debug mode after the instruction following the DEBUG instruction has entered the instruction latch.

10.6.6 Enabling Trace Mode

When the trace mode mechanism is enabled and the trace counter is greater than zero, the trace counter is decremented after each instruction execution. The completed execu- tion of an instruction when the trace counter is zero will cause the chip to enter the debug mode.

Note: Only instructions actually executed cause the trace counter to decrement, i.e. an aborted instruction will not decrement the trace counter and will not cause the chip to enter the debug mode.

10.6.7 Enabling Memory Breakpoints

When the memory breakpoint mechanism is enabled with a breakpoint counter value of zero, the chip enters the debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. In case of breakpoints on executed program memory fetches, the breakpoint will be acknowledged immediately after the execution of the fetched instruction. In case of breakpoints on data memory addresses (accesses to X, Y or P memory spaces by MOVE instructions), the breakpoint will be acknowledged after the completion of the instruction following the instruction that accessed the specified address.

10.7PIPELINE INFORMATION AND GLOBAL DATA BUS REGISTER

A number of on-chip registers store the chip pipeline status to restore the pipeline and re- sume normal chip activity upon return from the debug mode. Figure 10-8shows the block diagram of the pipeline information registers with the exception of the program address bus (PAB) registers, which are shown in Figure 10-9.

10.7.1 Program Data Bus Register (OPDBR)

The OPDBR is a 24-bit latch that stores the value of the program data bus which was gen- erated by the last program memory access before the chip entered the debug mode. OPDBR can be read or written through the OnCE serial interface. It is affected by the op- erations performed during the debug mode and must be restored by the external com- mand controller when the chip returns to normal mode.

MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 17