Motorola 24-Bit Digital Signal Processor, DSP56000 ADDRESS BUSES, 2- 4 DSP56K CENTRAL ARCHITECTURE OVERVIEW, , Figure 2-1 DSP56K Block Diagram, 2.3 ADDRESS BUSES,

ADDRESS BUSES
2- 4 DSP56K CENTRAL ARCHITECTURE OVERVIEW MOTOROLA
2.3 ADDRESS BUSES
Addresses are specified for internal X data memory and Y data memory on two unidirec-
tional 16-bit buses — X address bus (XAB) and Y address bus (YAB). Program memory
addresses are specified on the bidirectional program address bus (PAB). External mem-
CLOCK
GENERATOR
PERIPHERAL
PINS
INTERNAL
DATA
BUS
SWITCH
PROGRAM
RAM/ROM
EXPANSION
PROGRAM
INTERRUPT
CONTROLLER
PROGRAM
DECODE
CONTROLLER
PROGRAM
ADDRESS
GENERATOR
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODC/NMI
MODB/IRQB
RESET
DATA ALU
24X24+56→56-BIT MAC
TWO 56-BIT ACCUMULATORS
EXTERNAL
ADDRESS
BUS
SWITCH
BUS
CONTROL
EXTERNAL
DATA BU S
SWITCH
ADDRESS
DATA
16 BITS
24 BITS
PORT A
MODA/IRQA
PLL
X MEMORY
RAM/ROM
EXPANSION
Y MEMORY
RAM/ROM
EXPANSION
ADDRESS
GENERATION
UNIT
OnCE™
PERIPHERAL
MODULES
EXPANSION
AREA
CONTROL
24-Bit 56K
Module
Figure 2-1 DSP56K Block Diagram
Program Control Unit