Motorola 24-Bit Digital Signal Processor Operation with PLL Disabled, Changing the MF0-MF11 Bits

PLL OPERATION CONSIDERATIONS

4.For all input frequencies which would result in a VCO output frequency lower than the minimum specified in the device’s Technical Data Sheet (typically 10 MHz), PINIT must be cleared during hardware reset, disabling PLL operation. Otherwise, proper operation of the PLL cannot be guaranteed. If the resulting VCO clock frequency would be less than the minimum and the user wishes to operate with the PLL enabled, the user must issue an instruction which loads the PCTL control register with a multiplication factor that would bring the VCO frequency above 10 MHz and would enable the PLL operation. Until this instruction is executed, the PLL is disabled, which may cause a large skew (<15nsec) between the external input clock and the internal processor clock. If internal low frequency of operation is desired with the PLL enabled, the VCO output frequency may be divided down by using the internal low power divider.

5.The CKP pin only affects the CKOUT clock polarity during the hardware reset state. At the end of the hardware reset state, the CKP state is internally latched.

9.4.3Operation with PLL Disabled

1.If the PLL is disabled, the PLOCK pin is asserted.

2.If the PLL is disabled, the internal chip clock and CKOUT are driven from the EXTAL input.

9.4.4Changing the MF0-MF11 Bits

Changes to the MF0-MF11 bits cause the following to occur:

1.The PLL will lose the lock condition, the PLOCK pin will be deasserted.

2.The PLL acquires the proper phase/frequency. Until this occurs the internal chip clock phases will be frozen. This ensures that the clock used by the chip is a clock that has reached a stable frequency.

3.When lock occurs, PLOCK is asserted and the PLL drives the internal chip clock and CKOUT.

4.While PLL has not locked, CKOUT is held low if CKP is cleared. CKOUT is held high if CKP is set.

9.4.5Change of DF0-DF3 Bits

Changes to the DF0-DF3 bits do not cause a loss of lock condition. The internal clocks will immediately revert to the frequency prescribed by the new divide factor. For MF≤4, changing DF0-DF3 may lengthen the instruction cycle or CKOUT pulse following the PLL control register update in order to keep synchronization between EXTAL and the internal

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