INSTRUCTION DESCRIPTIONS
A - 64 INSTRUCTION SET DETAILS MOTOROLA
Operation: Assembler Syntax:
D[n] ➞ C; BTST #n,X:ea
D[n] ➞ C; BTST #n,X:aa
D[n] ➞ C; BTST #n,X:pp
D[n] ➞ C; BTST #n,Y:ea
D[n] ➞ C; BTST #n,Y:aa
D[n] ➞ C; BTST #n,Y:pp
D[n] ➞ C; BTST #n,D
Description: Test the nth bit of the destination operand D. The state of the nth bit is
stored in the carry bit C of the condition code register. The bit to be tested is selected by
an immediate bit number from 0–23. This instruction is useful for performing serial to par-
allel conversion when used with the appropriate rotate instructions. This instruction can
use all memory alterable addressing modes.
Example: :
BTST #$0,X:<<$FFEE ;read SSI serial input flag IF1 into C bit
ROL A ;rotate carry bit C into LSB of A1
:
Explanation of Example: Prior to execution, the 24-bit X location X:$FFEE (I/O SSI sta-
tus register) contains the value $000002. The execution of the BTST #$1,X:<<$FFEE
instruction tests the state of the 1st bit (serial input flag IF1) in X:$FFEE and sets the
carry bit C accordingly. This instruction sequence illustrates serial to parallel conversion
using the carry bit C and the 24-bit A1 register.
BTST Bit Test BTST
Before Execution After Execution
X:$FFEE X:$FFEE
$000002
SR SR
$0300 $0301
$000002