Motorola 24-Bit Digital Signal Processor, DSP56000 manual Compare Magnitude, Cmpm

INSTRUCTION DESCRIPTIONS

	CMPM	Compare Magnitude	CMPM
Operation:		Assembler Syntax:
	S2 – S1(parallel move)	CMPM	S1, S2 (parallel move)

Description: Subtract the absolute value (magnitude) of the source one operand, S1, from the absolute value of the source two accumulator, S2, and update the condition code register. The result of the subtraction operation is not stored.

Note: This instruction subtracts 56-bit operands. When a word is specified as S1, it is sign extended and zero filled to form a valid 56-bit operand. For the carry to be set cor- rectly as a result of the subtraction, S2 must be properly sign extended. S2 can be improperly sign extended by writing A1 or B1 explicitly prior to executing the compare so that A2 or B2, respectively, may not represent the correct sign extension. This note par- ticularly applies to the case where it is extended to compare 24-bit operands such as X0 with A1.

Example:

:

CMPM X1,A BA,L:–(R4)

:

Before Execution

A $00:000006:000000

A

;comp. Y0 and B, save X0, Y1

After Execution

$00:000006:000000

X1

$FFFFF7

X1

$FFFFF7

SR

$0300

SR

$0319

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $00:000006:000000, and the 24-bit X1 register contains the value $FFFFF7. The execution of the CMPM X1,A instruction automatically appends the 24-bit value in the X1 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, takes the absolute value of the resulting 56-bit number, subtracts the result from the absolute value of the contents of the 56-bit A accumulator, and updates the condition code regis- ter.

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