Motorola 24-Bit Digital Signal Processor, DSP56000 manual Logical Complement, Not

INSTRUCTION DESCRIPTIONS

	NOT		Logical Complement		NOT
Operation:				Assembler Syntax:
			➞ D[47:24] (parallel move)	NOT	D (parallel move)
		D[47:24]

where “—” denotes the logical NOT operator

Description: Take the ones complement of bits 47–24 of the destination operand D and store the result back in bits 47–24 of the destination accumulator. This is a 24-bit opera- tion. The remaining bits of D are not affected.

Example:
NOT A1 AB,L:(R2)+	;save A1,B1, take the ones complement of A1

A

Before Execution

$00:123456:789ABC

A

After Execution

$00:EDCBA9:789AB

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $00:123456:789ABC. The NOT A instruction takes the ones complement of bits 47–24 of the A accumulator (A1) and stores the result back in the A1 register. The remaining bits of the A accumulator are not affected.

Condition Codes:

15	14	13	12	11		10	9		8	7	6	5	4	3		2	1		0
LF	DM	T	**		S1	S0		I1	I0	S	L	E	U		N	Z		V	C
				MR										CCR

S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move

N — Set if bit 47 of A or B result is set

Z — Set if bits 47-24 of A or B result are zero

V — Always cleared

A - 242 INSTRUCTION SET DETAILS MOTOROLA