Motorola DSP56000, 24-Bit Digital Signal Processor manual Bclr

INSTRUCTION DESCRIPTIONS

BCLR

Bit Test and Clear

BCLR

Notes: If A or B is specified as the destination operand, the following sequence of events takes place:

1.The S bit is computed according to its definition (See Section A.5)

2.The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR).

3.If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set.

4.The resulting 24 bit value is placed back into A1 or B1. A0 or B0 is cleared and the sign of A1 or B1 is extended into A2 or B2.

5.The bit test and clear is performed on A1 or B1, and the C bit is set if the bit tested is set.

Timing: 4+mvb oscillator clock cycles

Memory: 1+ea program words

MOTOROLA INSTRUCTION SET DETAILS A - 55