Motorola DSP56000 manual Accumulator Shifter, Data Shifter/Limiter, Limiting Saturation Arithmetic

OVERVIEW AND DATA ALU ARCHITECTURE

shifting and limiting are not performed.

3.2.4 Accumulator Shifter

The accumulator shifter (see Figure 3-3)is an asynchronous parallel shifter with a 56-bit input and a 56-bit output that is implemented immediately before the MAC accumulator input. The source accumulator shifting operations are as follows:

•No Shift (Unmodified)

•1-Bit Left Shift (Arithmetic or Logical) ASL, LSL, ROL

•1-Bit Right Shift (Arithmetic or Logical) ASR, LSR, ROR

•Force to zero

3.2.5 Data Shifter/Limiter

The data shifter/limiter circuits (see Figure 3-3)provide special post-processing on data read from the Data ALU A and B accumulators out to the XDB or YDB. There are two in- dependent shifter/limiter circuits (one for XDB and one for the YDB); each consists of a shifter followed by a limiting circuit.

3.2.5.1Limiting (Saturation Arithmetic)

The A and B accumulators serve as buffer registers between the MAC unit and the XDB and/or YDB. They act both as Data ALU source and destination operands.Test logic exists in each accumulator register to support the operation of the data shifter/limiter circuits. This test logic detects overflows out of the data shifter so that the limiter can substitute one of several constants to minimize errors due to the overflow. This process is called sat- uration arithmetic

The Data ALU A and B accumulators have eight extension bits. Limiting occurs when the extension bits are in use and either A or B is the source being read over XDB or YDB. If the contents of the selected source accumulator can be represented without overflow in the destination operand size (i.e., accumulator extension register not in use), the data lim- iter is disabled, and the operand is not modified. If contents of the selected source accumulator cannot be represented without overflow in the destination operand size, the data limiter will substitute a limited data value with maximum magnitude (saturated) and with the same sign as the source accumulator contents: $7FFFFF for 24-bit or $7FFFFF

FFFFFFfor 48-bit positive numbers, $800000 for 24-bit or $800000 000000 for 48-bit neg- ative numbers. This process is called saturation arithmetic. The value in the accumulator register is not shifted and can be reused within the Data ALU. When limiting does occur, a flag is set and latched in the status register.Two limiters allow two-word operands to be limited independently in the same instruction cycle. The two data limiters can also be com-

MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 9