Motorola DSP56000 manual Stop Processing State, Simultaneous Wait Instruction and Interrupt

STOP PROCESSING STATE

INTERRUPT SYNCHRONIZED AND

RECOGNIZED AS PENDING

	INTERRUPT CONTROL CYCLE 1									i
	INTERRUPT CONTROL CYCLE 2										i
	FETCH	n3	n4	—	—	—	—	—		—	ii1	ii2	n4
	DECODE	n2	WAIT	—	—	—	—	—		—	—	ii1	ii2
	EXECUTE	n1	n2	WAIT	—	—	—		—	—	—	—	ii1
	INSTRUCTION CYCLE COUNT	1	2	3	4	5	6			7	8	9	10	11
i = INTERRUPT
ii = INTERRUPT INSTRUCTION WORD						EQUIVALENT TO
										EIGHT NOPs
n = NORMAL INSTRUCTION WORD

Figure 7-16 Simultaneous Wait Instruction and Interrupt

7.6STOP PROCESSING STATE

The STOP instruction brings the processor into the stop processing state, which is the lowest power consumption state. In the stop state, the clock oscillator is gated off; whereas, in the wait state, the clock oscillator remains active. The chip clears all periph- eral interrupts and external interrupts (IRQA, IRQB, and NMI) when it enters the stop state. Trace or stack errors that were pending, remain pending. The priority levels of the peripherals remain as they were before the STOP instruction was executed. The on-chip peripherals are held in their respective individual reset states while in the stop state.

MOTOROLA PROCESSING STATES 7 - 37