Motorola DSP56000, 24-Bit Digital Signal Processor manual Condition Codes

INSTRUCTION DESCRIPTIONS

BCLR

Bit Test and Clear

BCLR

Explanation of Example: Prior to execution, the 24-bit X location X:$FFE4 (I/O port B data register) contains the value $FFFFFF. The execution of the BCLR #$E,X:<<$FFE4 instruction tests the state of the 14th bit in X:$FFE4, sets the carry bit C accordingly, and then clears the 14th bit in X:$FFE4.

Condition Codes:

15	14	13	12	11		10	9		8	7	6	5	4	3	2	1		0
LF	DM	T	**		S1	S0		I1	I0	S	L	E	U	N	Z		V	C
				MR									CCR

CCR Condition Codes:

For destination operand SR:

C — Cleared if bit 0 is specified. Not affected otherwise.

V — Cleared if bit 1 is specified. Not affected otherwise.

Z — Cleared if bit 2 is specified. Not affected otherwise.

N — Cleared if bit 3 is specified. Not affected otherwise.

U — Cleared if bit 4 is specified. Not affected otherwise.

E — Cleared if bit 5 is specified. Not affected otherwise.

L — Cleared if bit 6 is specified. Not affected otherwise.

S — Cleared if bit 7 is specified. Not affected otherwise.

For destination operand A or B:

S —Computed according to the definition. See Notes on page A-55.L — Set if data limiting has occurred. See Notes on page A-55.

E — Not affected

U — Not affected

N — Not affected

Z — Not affected

V — Not affected

C — Set if bit tested is set. Cleared otherwise.

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