Motorola DSP56000 manual OnCE Decoder Odec, OnCE Status and Control Register Oscr, MBO SWO TME BC3

OnCE CONTROLLER AND SERIAL INTERFACE

shifted in (so a new command is available) and the second indicating that 24 bits were shifted in (the data associated with that command is available) or that 24 bits were shifted out (the data required by a read command was shifted out).

10.3.3 OnCE Decoder (ODEC)

The ODEC supervises the entire OnCE activity. It receives as input the 8-bit command from the OCR, two signals from OBC (one indicating that 8 bits have been received and the other that 24 bits have been received), and two signals indicating that the processor was halted. The ODEC generates all the strobes required for reading and writing the se- lected OnCE registers.

10.3.4 OnCE Status and Control Register (OSCR)

The Status and Control Register is a 16-bit register used to select the events that will put the chip in debug mode and to indicate the reason for entering debug mode. The control bits are read/write while the status bits are read only. See Figure 10-5.

10.3.4.1Memory Breakpoint Control (BC0-BC3) Bits 0-3

These control bits enable memory breakpoints. They allow memory breakpoints to occur when a memory address is within the low and high memory address registers and will se- lect whether the breakpoint will be recognized for read, write, or fetch (program space) accesses. These bits are cleared on hardware reset. See Table 10-3for the definition of the BC0-BC3 bits.

When BC3-BC0=0001, program memory breakpoints are enabled for any fetch access to the program space (true and false fetches, fetches of 2nd word, etc.). Explicit program memory accesses resulting from MOVEP and MOVEM instructions to/from program memory space are ignored.

When BC3-BC0=0010, program memory breakpoints are enabled for any read access to the Program space (MOVEP and MOVEM instructions from P: memory space, true and false fetches, fetches of 2nd word, etc.). Explicit program memory write accesses resulting from MOVEP and MOVEM instructions to P: memory space are ignored.

15	....	11 10		9 8		7	6	5	4 3		2	1	0
	*		TO	MBO	SWO	*	*	*	TME	BC3	BC2	BC1	BC0

* Reserved, read as zero, should be written with zero for future compatibility.

Figure 10-5 OnCE Status and Control Register (OSCR)

10- 10 ON-CHIP EMULATION (OnCE) MOTOROLA