Motorola DSP56000, 24-Bit Digital Signal Processor manual Motorola, List of Figures Vii Revision

LIST of FIGURES

Figure				Page
Number			Title	Number
1-1	Analog Signal Processing		. . 1-4
	1-2	Digital Signal Processing		. . 1-5
	1-3	DSP Hardware Origins		. . 1-9
	2-1	DSP56K Block Diagram		. . 2-4
	3-1	DSP56K Block Diagram		. . 3-4
	3-2	Data ALU		. . 3-5
	3-3	MAC Unit		. . 3-7
	3-4	DATA ALU Accumulator Registers	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 3-8
	3-5	Saturation Arithmetic		. . 3-10
	3-6	Integer-to-Fractional Data Conversion		. . 3-11
	3-7	Bit Weighting and Alignment of Operands		. . 3-12
	3-8	Integer/Fractional Number Comparison		. . 3-13
	3-9	Integer/Fractional Multiplication Comparison		. . 3-14
	3-10	Convergent Rounding		. . 3-15
	3-11	Full Double Precision Multiply Algorithm		. . 3-16
	3-12	Single X Double Multiply Algorithm		. . 3-17
	3-13	Single X Double Multiply-Accumulate Algorithm		. . 3-18
	3-14	DSP56K Programming Model		. . 3-19
	4-1	DSP56K Block Diagram		. . 4-4
	4-2	AGU Block Diagram		. . 4-5
	4-3	AGU Programming Model		. . 4-7
	4-4	Address Register Indirect — No Update		. 4-10
	4-5	Address Register Indirect — Postincrement		. 4-11
	4-6	Address Register Indirect — Postdecrement		. 4-12
	4-7	Address Register Indirect — Postincrement by Offset Nn		. 4-13
	4-8	Address Register Indirect — Postdecrement by Offset Nn		. 4-14
	4-9	Address Register Indirect — Indexed by Offset Nn		. 4-15
	4-10	Address Register Indirect — Predecrement		. 4-16
	4-11	Circular Buffer		. . 4-19
	4-12	Linear Addressing with a Modulo Modifier		. . 4-20
	4-13	Modulo Modifier Example		. . 4-21

MOTOROLA	LIST of FIGURES	vii
Revision 2.1	DSP56004 DESIGN SPECIFICATION	vii