Motorola 24-Bit Digital Signal Processor, DSP56000 manual Isbkpt, Memory Lower Limit Register Omllr

OnCE MEMORY BREAKPOINT LOGIC

DSCK		PAB	XAB	YAB
DSO	DSI
		MEMORY ADDRESS LATCH			MEMORY BUS SELECT
		HIGH ADDRESS COMPARATOR
				LOWER	BC3-BC0
	.			OR
.				EQUAL
		UPPER LIMIT REGISTER
					MEMORY
					BREAKPOINT
		LOW ADDRESS COMPARATOR			SELECTION
				HIGHER
	.			OR
.				EQUAL
		LOWER LIMIT REGISTER			BREAKPOINT
.	.			DEC	.OCCURRED
		BREAKPOINT COUNTER
		COUNT=0			.

ISBKPT

Figure 10-6 OnCE Memory Breakpoint Logic

10.4.2 Memory Upper Limit Register (OMULR)

The 16-bit Memory Upper Limit Register stores the memory breakpoint upper limit. The OMULR can be read or written through the OnCE serial interface. Before enabling break- points, OMULR must be loaded by the external command controller.

10.4.3 Memory Lower Limit Register (OMLLR)

The 16-bit Memory Lower Limit Register stores the memory breakpoint lower limit. The OMLLR can be read or written through the OnCE serial interface. Before enabling break-

MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 13