OnCE MEMORY BREAKPOINT LOGIC
MOTOROLA
ON-CHIP EMULATION (OnCE) 10 - 13
10.4.2 Memory Upper Limit Register (OMULR)
The 16-bit Memory Upper Limit Register stores the memory breakpoint upper limit. The
OMULR can be read or written through the OnCE serial interface. Before enabling break-
points, OMULR must be loaded by the external command controller.
10.4.3 Memory Lower Limit Register (OMLLR)
The 16-bit Memory Lower Limit Register stores the memory breakpoint lower limit. The
OMLLR can be read or written through the OnCE serial interface. Before enabling break-
.
MEMORY ADDRESS LATCH
PAB XAB YAB
MEMORY BUS SELECT
LOWER LIMIT REGISTER
LOW ADDRESS COMPARATOR
UPPER LIMIT REGISTER
HIGH ADDRESS COMPARATOR
HIGHER
DSI
DSO
DSCK
BREAKPOINT COUNTER
OR
EQUAL
LOWER
OR
EQUAL
MEMORY
BREAKPOINT
SELECTION
BC3-BC0
DEC
BREAKPOINT
COUNT=0
ISBKPT
OCCURRED
.
.
.
..
.
.
Figure 10-6 OnCE Memory Breakpoint Logic