Motorola DSP56000, 24-Bit Digital Signal Processor manual Fast Interrupt Service Routine

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING

ADDITIONAL INTERRUPTS DISABLED DURING FAST INTERRUPT

INTERRUPTS

RE-ENABLED

MAIN

PROGRAM

MEMORY

n1

n2

n3

n4

ii1

ii2

ii= INTERRUPT INSTRUCTION n = NORMAL INSTRUCTION

(a)Instruction Fetches from Memory

INTERRUPT SYNCHRONIZED AND

RECOGNIZED AS PENDING

INTERRUPTS RE-ENABLED

INTERRUPT CONTROL CYCLE 1	i
INTERRUPT CONTROL CYCLE 2		i
FETCH	n1	n2	ii1	ii2	n3	n4
DECODE		n1	n2	ii1	ii2	n3	n4
EXECUTE			n1	n2	ii1	ii2	n3	n4
INSTRUCTION CYCLE COUNT	1	2	3	4	5	6	7	8

i= INTERRUPT

ii= INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD

(b)Program Controller Pipeline

Figure 7-8 Fast Interrupt Service Routine

MOTOROLA PROCESSING STATES 7 - 27