Motorola DSP56000, 24-Bit Digital Signal Processor Address Register Indirect Indexed by Offset Nn

ADDRESSING

EXAMPLE: MOVE Y1,X: (R6+N6)

BEFORE EXECUTION AFTER EXECUTION

	Y1			Y0
47	24	23					0
6	2 1 0 0 9	B A 4 C 2 2
23	0	23					0
		23	X MEMORY				0
	$6004
		X	X	X	X	X	X
	$6000	X	X	X	X	X	X

15	0
	$6000
R6

15		0	+
		$0004
	N6
15		0
		$FFFF
M6

Assembler Syntax: (Rn+Nn)

Memory Spaces: P:, X:, Y:, L:

Additional Instruction Execution Time (Clocks): 2

Additional Effective Address Words: 0

	Y1							Y0
47	24		23							0
6	2 1 0 0 9		B A 4 C 2 2
23	0		23							0
			23		X MEMORY					0
		$6004
			$		6	2		1 0	0	9
	$6000		X		X		X	X	X	X
						15				0
				R6				$6000
						15				0

N6 $0004

150

M6 $FFFF

Figure 4-9 Address Register Indirect — Indexed by Offset Nn

The contents of the address modifier register, Mn, defines the type of arithmetic to be per- formed for addressing mode calculations. For modulo arithmetic, the contents of Mn also specifies the modulus, or the size of the memory buffer whose addresses will be refer- enced. See Table 4-2for a summary of the address modifiers implemented on the

MOTOROLA ADDRESS GENERATION UNIT 4 - 15