Motorola 24-Bit Digital Signal Processor, DSP56000 manual Area

PLL COMPONENTS

								EXPANSION
								AREA
	PERIPHERAL			PROGRAM		X MEMORY	Y MEMORY
				RAM/ROM		RAM/ROM	RAM/ROM
		MODULES
PERIPHERAL PINS				EXPANSION		EXPANSION	EXPANSION
			ADDRESS		YAB			EXTERNAL	ADDRESS
					XAB
		GENERATION						ADDRESS
	24-Bit				PAB
			UNIT					BUS
	56K Mod-							SWITCH
										A
								BUS	CONTROL	PORT
								CONTROL
					YDB
	INTERNAL				XDB			EXTERNAL	DATA
	DATA							DATA BUS
	BUS				PDB			SWITCH
	SWITCH
					GDB
	PLL					DATA ALU
		PROGRAM	PROGRAM	PROGRAM
						24X24+56→56-BIT MAC		OnCE™
	CLOCK	INTERRUPT	DECODE	ADDRESS
		CONTROLLER	CONTROLLER	GENERATOR	TWO 56-BIT ACCUMULATORS
	GENERATOR
			Program Control Unit
			MODC/NMI

16 BITS

MODB/IRQB	24 BITS
MODA/IRQA

RESET

Figure 9-2 DSP56K Block Diagram

9.2.1Phase Detector and Charge Pump Loop Filter

The Phase Detector (PD) detects any phase difference between the external clock (EXTAL) and an internal clock phase from the frequency multiplier. At the point where there is negligible phase difference and the frequency of the two inputs is identical, the PLL is in the “locked” state.

9 - 4 PLL CLOCK OSCILLATOR MOTOROLA