Motorola 24-Bit Digital Signal Processor, DSP56000 PLL COMPONENTS, 9 - 4 PLL CLOCK OSCILLATOR, , Figure 9-2 DSP56K Block Diagram, 9.2.1 Phase Detector and Charge Pump Loop Filter,

PLL COMPONENTS
9 - 4 PLL CLOCK OSCILLATOR MOTOROLA
9.2.1 Phase Detector and Charge Pump Loop Filter
The Phase Detector (PD) detects any phase difference between the external clock
(EXTAL) and an internal clock phase from the frequency multiplier. At the point where
there is negligible phase difference and the frequency of the two inputs is identical, the
PLL is in the “locked” state.
CLOCK
GENERATOR
PERIPHERAL
PINS
INTERNAL
DATA
BUS
SWITCH
PROGRAM
RAM/ROM
EXPANSION
PROGRAM
INTERRUPT
CONTROLLER
PROGRAM
DECODE
CONTROLLER
PROGRAM
ADDRESS
GENERATOR
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODC/NMI
MODB/IRQB
RESET
DATA ALU
24X24+56→56-BIT MAC
TWO 56-BIT ACCUMULATORS
EXTERNAL
ADDRESS
BUS
SWITCH
BUS
CONTROL
EXTERNAL
DATA BU S
SWITCH
ADDRESS
DATA
16 BITS
24 BITS
PORT A
MODA/IRQA
PLL
X MEMORY
RAM/ROM
EXPANSION
Y MEMORY
RAM/ROM
EXPANSION
ADDRESS
GENERATION
UNIT
OnCE™
PERIPHERAL
MODULES
EXPANSION
AREA
CONTROL
24-Bit
56K Mod-
Figure 9-2 DSP56K Block Diagram
Program Control Unit