AGU ARCHITECTURE
MOTOROLA
ADDRESS GENERATION UNIT 4 - 5
GDB. When read by the GDB, the contents of a register are placed in the two least signif-
icant bytes, and the most significant byte on the GDB is zero extended. When a register
is written, only the least significant 16 bits of the GDB are used; the upper portion is
truncated.
4.2.3 Modifier Register Files (Mn)
Each of the two modifier register files shown in Figure 4-2 consists of four 16-bit registers.
The two files contain modifier registers M0 - M3 and M4 - M7, which specify the type of
arithmetic used during address register update calculations or contain data. Each modifier
register can be read or written by the GDB. When read by the GDB, the contents of a reg-
ister are placed in the two least significant bytes, and the most significant byte on the GDB
is zero extended. When a register is written, only the least significant 16 bits of the GDB
are used; the upper portion is truncated. Each modifier register is preset to $FFFF during
a processor reset.
4.2.4 Address ALU
The two address ALUs are identical (see Figure 4-2) in that each contains a 16-bit full
adder (called an offset adder), which can add 1) plus one, 2) minus one, 3) the contents
of the respective offset register N, or 4) the twos complement of N to the contents of the
GLOBAL DATA BUS
N0
N1
N2
N3 M3
M2
M1
M0
ADDRESS
ALU ADDRESS
ALU
R0
R1
R2
R3 R7
R6
R5
R4 M4
M5
M6
M7 N7
N6
N5
N4
TRIPLE MULTIPLEXER
LOW ADDRESS ALU HIGH ADDRESS ALU
XAB YAB PAB
16 bits
24 bits
Figure 4-2 AGU Block Diagram