CONDITION CODE COMPUTATION

S1

S0

Scaling Mode

Signed Integer Portion

0

0

No Scaling

Bits 55, 54, . . . . 48, 47

0

1

Scale Down

Bits 55, 54, . . . . 49, 48

1

0

Scale Up

Bits 55, 54, . . . . 47, 46

Note that the signed integer portion of an accumulator IS NOT necessarily the same as the extension register portion of that accumulator. The signed integer portion of an accu- mulator consists of the MS 8, 9, or 10 bits of that accumulator, depending on the scaling mode being used. The extension register portion of an accumulator (A2 or B2) is always the

MS 8 bits of that accumulator. The E bit refers to the signed integer portion of an accu- mulator and NOT the extension register portion of that accumulator. For example, if

the current scaling mode is set for no scaling (i.e., S1=S0=0), the signed integer portion of the A or B accumulator consists of bits 47 through 55. If the A accumulator contained the signed 56-bit value $00:800000:000000 as a result of a data ALU operation, the E bit would be set (E=1) since the 9 MS bits of that accumulator were not all the same (i.e., nei- ther 00 . . 00 nor 11 . . 11). This means that data limiting will occur if that 56-bit value is specified as a source operand in a move-type operation. This limiting operation will result in either a positive or negative, 24-bit or 48-bit saturation constant being stored in the specified destination. The only situation in which the signed integer portion of an accumulator and the extension register portion of an accumulator are the same is in the “Scale Down” scaling mode (i.e., S1=0 and S0=1).

U (Unnormalized Bit)

Set if the two MS bits of the MSP portion of the A or B result are the

 

same. Cleared otherwise. The MSP portion is defined by the scal-

 

ing mode. The U bit is computed as follows:

 

S1

S0

Scaling Mode

U Bit Computation

 

0

0

No Scaling

 

 

 

 

 

 

 

U=(Bit 47

Bit 46)

 

 

0

1

Scale Down

 

 

 

 

 

 

U=(Bit 48

Bit 47)

 

 

1

0

Scale Up

 

 

 

 

 

U=(Bit 46

Bit 45)

N (Negative Bit)

Set if the MS bit 55 of the A or B result is set. Cleared otherwise.

Z (Zero Bit)

Set if the A or B result equals zero. Cleared otherwise.

V (Overflow Bit)

Set if an arithmetic overflow occurs in the 56-bit A or B result. This

 

indicates that the result cannot be represented in the 56-bit accu-

 

mulator; thus, the accumulator has overflowed. Cleared otherwise.

MOTOROLA

INSTRUCTION SET DETAILS

A - 17

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Motorola DSP56000, 24-Bit Digital Signal Processor manual Scaling Mode Signed Integer Portion, Scaling Mode Bit Computation