Motorola 24-Bit Digital Signal Processor, DSP56000 manual Xea D1 S2 D2 Xea,D1

INSTRUCTION DESCRIPTIONS

X:R X Memory and Register Data Move X:R

Operation:		Assembler Syntax:
Class I		Class I
(	); X:ea➞D1; S2➞D2	(	) X:ea,D1	S2,D2
(	); S1➞X:ea; S2➞D2	(	) S1,X:ea	S2,D2
(	); #xxxxxx➞D1; S2➞D2	(	) #xxxxxx,D1 S2,D2

Class II		Class II
(	); A➞X:ea; X0➞A	(	) A,X:ea	X0,A
(	); B➞X:ea; X0➞B	(	) B,X:ea	X0,B
where ( . . . .	. ) refers to any arithmetic or logical instruction which allows parallel moves.

Description: Class I: Move a one-word operand from/to X memory and move another word operand from an accumulator (S2) to an input register (D2). All memory addressing modes, including absolute addressing and 24-bit immediate data, may be used. The reg- ister to register move (S2,D2) allows a data ALU accumulator to be moved to a data ALU input register for use as a data ALU operand in the following instruction.

Class II: Move one-word operand from a data ALU accumulator to X memory and one- word operand from data ALU register X0 to a data ALU accumulator. One effective address is specified. All memory addressing modes, excluding long absolute addressing and long immediate data, may be used.

For both Class I and Class II X:R parallel data moves, if the arithmetic or logical opcode- operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination D1 in the parallel data bus move operation. Thus, if the opcode-operand portion of the instruc- tion specifies the 56-bit A accumulator as its destination, the parallel data bus move por- tion of the instruction may not specify A0, A1, A2, or A as its destination D1. Similarly, if the opcode-operand portion of the instruction specifies the 56-bit B accumulator as its destination, the parallel data bus move portion of the instruction may not specify B0, B1, B2, or B as its destination D1. That is, duplicate destinations are NOT allowed within the same instruction.

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