Motorola DSP56000 manual Normal Processing State, Instruction Pipeline, Instruction Pipelining

PROCESSING STATES

7.1PROCESSING STATES

The DSP56K processor is always in one of five processing states: normal, exception, reset, wait, or stop. This section describes each of the processing states.

7.2NORMAL PROCESSING STATE

The normal processing state is associated with instruction execution. Details about nor- mal processing of the individual instructions can be found in APPENDIX A - INSTRUC- TION SET DETAILS. Instructions are executed using a three-stage pipeline, which is described in the following paragraphs.

7.2.1 Instruction Pipeline

DSP56K instruction execution occurs in a three-stage pipeline, which allows most instructions to execute at a rate of one instruction per instruction cycle. However, certain instructions require additional time to execute: instructions longer than one word, instruc- tions using an addressing mode that requires more than one cycle, and instructions that cause a control-flow change. In the latter case, a cycle is needed to clear the pipeline.

Pipelining allows instruction executions to overlap so that the fetch-decode-execute operations of a given instruction occur concurrently with the fetch-decode-execute oper- ations of other instructions. Specifically, while the processor is executing one instruction, it is decoding the next instruction, and fetching the next instruction from program mem- ory. The processor fetches only one word per cycle, so if an instruction is two words in length, it fetches the additional word before it fetches the next instruction.

Table 7-1demonstrates pipelining. F1, D1, and E1 refer to the fetch, decode, and exe- cute operations, respectively, of the first instruction. The third instruction, which contains an instruction extension word, takes two instruction cycles to execute. The extension word will be either an absolute address or immediate data. Although it takes three instruction cycles for the pipeline to fill and the first instruction to execute, an instruction usually executes on each instruction cycle thereafter.

Table 7-1 Instruction Pipelining

Operation					Instruction Cycle
	1	2	3	4		5	6	7	•	•	•
Fetch	F1	F2	F3	F3e		F4	F5	F6	•	•	•
Decode		D1	D2	D3		D3e	D4	D5	•	•	•
Execute			E1	E2		E3	E3e	E4	•	•	•

MOTOROLA PROCESSING STATES 7 - 3